1. Field of the Invention
The present invention relates to a power-on detection circuit for detecting a state that a supplied voltage has reached to a constant potential, in a period when a power supply is initiated.
2. Description of the Related Art
A circuit for detecting a power-on voltage of power supply (hereinafter called “the power-on detection circuit”) has been widely used in a semiconductor device including a memory, for example, as described in Japanese Laid Open Patent Application (JP-P 2001-127609A).
A conventional power-on detection circuit, which corresponds to a circuit portion surrounded with a box of dashed line in FIG. 1, is known. That is, in the circuit configuration where a series circuit consisting of a first dividing resistor R1 and a second dividing resistor R2 is inserted between a first power supply Vdd and a second power supply (ground wiring) Vss of, the second power supply provides a lower potential Vss than the potential Vdd of the first power supply, by feeding a current so as to flow through the first dividing resistor R1 and the second dividing resistor R2, a certain desirable potential is obtained from a node between the first dividing resistor R1 and the second dividing resistor R2, by voltage division across the first dividing resistor R1 and the second dividing resistor R2. In order to attain a smaller current which can satisfy a circuit requirement, the resistance values of the first dividing resistor R1 and the second dividing resistor R2 inevitably have the large values determined from the circuit requirement for a semiconductor chip on which a plurality of semiconductor elements are integrated.
Moreover, as shown in the circuit portion surrounded with the box of dashed line of FIG. 1, the node between the first dividing resistor R1 and the second dividing resistor R2 is connected to a gate electrode of a pMOS transistor whose source electrode is connected to the first power supply Vdd. On the other hand, a drain resistor R4 is inserted between a drain electrode of the pMOS transistor and the second power supply (ground wiring) Vss. The potential determined by the voltage division across the first dividing resistor R1 and the second dividing resistor R2 is applied to the gate electrode of the pMOS transistor. Thus, as the potential Vdd of the first power supply increases, a potential difference across the source electrode and the gate electrode becomes larger. Then, at a certain potential Vdd, the pMOS transistor is turned on, thereby detecting the power-on potential.
However, the threshold voltage of the pMOS transistor has temperature dependence. Also, even under a constant temperature, the threshold voltages vary in different semiconductor chips and for different wafers. Thus, there was a problem that, when the power-on was detected, the power-on potential of the first power supply Vdd scatters with semiconductor chips and wafers. Moreover, there was a problem that, when a ratio of a resistance value between the first dividing resistor R1 and the second dividing resistor R2 was, for example, 1:2, the variation in the threshold voltage of the pMOS transistor was amplified to three times, which affects the power-on potential.